Wednesday, December 11, 2013

Tuesday, August 13, 2013

to read

A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing

http://www2.cose.isu.edu/~zydedawi/Research/publications.php

Wednesday, March 6, 2013

Differences between AXI Streaming and FSL

According to the UG761 AXI Reference Guide, the mapping of FSL Signals to AXI Streaming Signals is as follows:




But in actual fact, M_AXIS_TREADY = ! FSL_M_FULL, since it's active high. The rest of the signals has a direct one to one mapping.

Also there is slight handshaking difference.
The AXI_M_TVALID signal cannot be deasserted after being asserted unless a transfer is
completed with AXI_TREADY. However, a AXI_TREADY can be asserted and deasserted
whenever the AXI4-Stream slave requires assertion and deassertion.

A master is not permitted to wait until TREADY is asserted before asserting TVALID. Once
TVALID is asserted it must remain asserted until the handshake occurs.

That means what in FSL
 if (!M_FULL)
   M_Write


looks like this in AXI Streaming Masters.
M_Write
wait until !M_FULL

References:
AMBA 4 AXI4-Stream Protocol Specification
UG761 AXI Reference Guide